Over the past several years, memory systems, particularly in the personal computer (PC) sector, have seen a dramatic increase in data bandwidth requirements. One industry segment that has experienced significant growth as a result of this increase in data bandwidth requirements is dynamic random access memory (DRAM), particularly double data rate (DDR) synchronous DRAM (SDRAM). DDR memory architectures use both the rising and falling edges of a clock signal to access memory, which facilitates data transmission at twice the standard clock rate. DDR SDRAM also consumes less power than conventional SDRAM, with an operational supply voltage of about 2.5 volts, instead of 3.3 volts for SDRAM.
DDR memory's ability to transfer data at double the standard SDRAM data rate often imposes significant challenges on memory system designers. The speeds at which a memory controller must reliably operate (e.g., 400 megahertz (MHz) across traces on a typical woven glass reinforced epoxy resin printed circuit board (PCB)) make PCB layout particularly challenging. Moreover, incorporating a DDR memory interface into a flexible field programmable gate array (FPGA) fabric presents the designer with the related complexity of meeting very critical and tight timing constraints in an inherently non-deterministic routing fabric. The difficulties often encountered arise predominantly from the physical realities of working with data windows that are well within the magnitude of signal propagation delays in PCB and FPGA routing (e.g., about 2.5 nanoseconds (ns) or less for a 400 MHz clock). These timing requirements are further complicated by the variation in logic speed over process, voltage and/or temperature (PVT) conditions to which the memory system may be subjected. The memory system designer can no longer simply connect data lines and address lines and expect to have a robust, high-speed memory interface.
Depending on the layout of the memory system on a PCB and on the number of banks of memory employed, if a memory controller must fetch data from a large number of banks concurrently, the difference in board delays between the various memory banks and the controller can often exceed one clock cycle, thereby increasing latency in the memory system. One known approach which attempts to address this issue is to compute a round trip (RT) delay value for each memory bank in the system, and to store the various RT delay values in a register. A programmable delay line is then utilized in the memory system for selectively delaying a read strobe signal based on the computed RT delay value(s) corresponding to the memory bank(s) being read. This approach, however, requires an initialization procedure for determining the RT delay value of each memory bank, and additionally requires a programmable delay line which significantly increases the cost of the memory system. Moreover, this approach does not adjust for variations in certain operating characteristics of the memory system, such as, for example, supply voltage and/or temperature, which may occur after the RT delay values have been determined.
Accordingly, there exists a need for techniques for reducing read strobe latency in a memory system that does not suffer from one or more of the problems exhibited by conventional memory systems.